Internal Memory - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

For AMD programmable logic devices, on-chip memory primitives come in three sizes: small, medium, and large. These memory primitives serve as the building blocks that allow users to build a wide range of memory structures. They are commonly referred to as distributed RAM, block RAM, and UltraRAM.

Distributed RAM primitives are the smallest building blocks and are widely available throughout the device. The 6-input dual-output LUTs in AMD devices can be configured as synchronous RAM and can be stitched together to build large memory arrays. See UltraScale Architecture Configurable Logic Block User Guide (UG574) or Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005) for further information.

Block RAM primitives are medium sized building blocks. Each block RAM is a 36 kb true dual-port memory up to 72-bits wide. The 36 kb can be split into two 18 kb depending on the needs of the design. UltraRAM primitives are the large building blocks. UltraRAM are 288 kb single clock synchronous memory up to 72-bits wide. See UltraScale Architecture Memory Resources User Guide (UG573) or Versal Adaptive SoC Memory Resources Architecture Manual (AM007) for further information.

Table 1. On-Chip Memory Summary
Type Size UltraScale+ Device Configurations Versal Device Configurations
Distributed RAM 64 bit Various Various
Block RAM 36 kb, 18 kb 32 kb x 1, 16 kb x 2,

8 kb x 4, 4 kb x 9,

2 kb x 18, 1 kb x 36

4 kb x 9, 2 kb x 18, 1 kb x 36
UltraRAM 288 kb 4 kb x 72 32 kb x 9, 16 kb x 18,

8 kb x 36, 4 kb x 72