Working with AMD IP consists of first customizing an IP for use in an RTL design. You can create an IP customization in various ways using the AMD Vivado™ Design Suite, as follows:
- Directly customizing an IP into a project from the IP catalog.
- Using the Manage IP project flow to create a stand-alone customization of an IP for use in the current project and others.
- Using a Tcl script to create an IP customization in either project or non-project mode.
- Using block designs (BDs). The IP integrator is a block design, that is a visual representation of a hardware design that can be used to connect and configure IP cores. IP integrator is used for generating and quickly connecting multiple IP blocks regardless of the complexity.
Inference is supported as well (see the Vivado Design Suite User Guide: Synthesis (UG901)).
Whichever flow you prefer, AMD is ready to help you learn and understand any of the Vivado Design Suite features. For QuickTake video tutorials that walk you through the various flows, see Vivado overview website. For comprehensive training classes, see the Training website.
Designing with IP User Guide
The Vivado Design Suite User Guide: Designing with IP (UG896) ) is a comprehensive guide that covers how to use the IP integrator in the Vivado Design Suite to create custom designs using pre-defined intellectual property (IP) cores. The guide covers everything from the basics of IP integration to advanced topics such as customizing IP, modifying constraints, and creating custom IP blocks. It also provides step-by-step instructions for using the IP integrator, and includes a number of helpful tips and tricks for designing with IP. Overall, the guide is a great resource for anyone looking to design custom hardware using IP cores in the Vivado Design Suite.
Designing with IP Tutorial
The Vivado Design Suite Tutorial: Designing with IP (UG939) is a comprehensive guide that teaches you how to design custom FPGA designs using the Vivado Design Suite. The tutorial covers all aspects of the design process starting from creating a new project, selecting and customizing IP blocks, integrating IP blocks into the project, running synthesis and implementation, debugging, and exporting the design. It provides step-by-step instructions and examples to help you understand the process and create successful FPGA implementations. The tutorial aims to familiarize you with the Vivado Design Suite and simplify the process of designing and customizing IP blocks.
Designing IP Subsystems Using IP Integrator
The Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) provides system designers with an in-depth guide on how to create and integrate IP subsystems using the IP integrator in the Vivado Design Suite. The document provides step-by-step instructions and examples to ensure successful IP subsystem implementation. The IP integrator is a powerful alternate to the Altera platform designer. It enables the use of processors, interfaces to off-chip processors, standard peripherals, IP cores, on-chip memory, off-chip memory, and user-defined logic into a custom system module.
Creating and Packaging Custom IP
The Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118) provides system designers with a detailed, step-by-step guide to create, package, and integrate custom IP in the Vivado Design Suite. The document guides you to a successful IP implementation and contributes to efficient customization and reusability in your design projects.
Intellectual Property Selection
AMD and partners have a rich library of intellectual property to help you get to market faster. AMD IP goes through vigorous test and validation to help you have success the first time. Beyond a simple library of cores, AMD provides other solutions to increase your productivity. The IP integrator is a GUI that enables rapid connection of IP, which is enabled by a common AXI-based user interface. This process can reduce the design effort by months. AMD also has IP subsystems that integrate multiple IP into one solution. Why generate a DMA and PCIe core when an AMD IP subsystem delivers it for you. AMD has many other subsystems. Why worry about peripheral interfaces? Let AMD help you get to market faster. Allowing you to focus on your application design. AMD IP solutions are designed to make you more productive.
IP Constraints
IP are validated with the constraints that are delivered with them. In some cases, an IP delivered constraint might need to be changed. You can edit the IP XDC using the method described in Editing IP Sources. Alternatively, you can override the IP XDC command by providing a top-level user XDC or a Tcl file with the desired commands.