I/O - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

The I/O conversion method depends on the type of flow used to insert the I/O buffer:

  • For converting instantiated I/O primitives, the instances must be modified to match the equivalent AMD I/O primitives.
  • Vivado synthesis or Vivado opt_design infers I/O buffers and 3-state I/Os in cases where no pads are directly instantiated. Ensure that the proper constraints are in place for the I/O standards associated with the inferred I/O.
  • For I/O associated with high-level IP functions (transceivers, Ethernet, PCIe, etc.) this I/O conversion takes place with the associated high-level IP conversion. See the appropriate sections in this guide for further information.