I/O Planning - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

AMD FPGAs and adaptive SoCs support a wide range of I/O standards and voltage levels, offering flexibility across various applications. To ensure that the devices you are considering meet your specific I/O requirements, it is essential to consult the relevant documentation for each FPGA family. These documents provide detailed information on the I/O capabilities, including supported standards, voltage ranges, and configuration options. Each device family has unique I/O features, which can be configured by banks to accommodate different voltage levels and modes.

When converting a design to AMD FPGAs, the designer needs to be aware of the bank voltage specifications, constraints, and limitations. Properly understanding these aspects ensures your design functions as expected in the target FPGA. For seamless integration, make use of the following resources to verify and validate I/O functionality:

  • Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
  • Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
  • UltraScale Architecture SelectIO Resources User Guide (UG571)
  • 7 Series FPGAs SelectIO Resources User Guide (UG471)

Clocking

Most details about clocking are found in the Clocking section of this document.