Device input clocks must be on one of four global clock (GC) pins per bank, which have access to the global clock resources (MMCM, PLLs and global clock buffers). Some Versal devices can have HDIO banks with two GC pins per bank. The GC pins are found in the package file under the pin name column (see UltraScale or Versal). Look for *GC* in the column; polarity is also included in same column with *P* or *N*. There are restrictions about which GC pins can access which clock management primitives around the device through dedicated clock routing (best solution vs. programmable logic routing). See the CLOCK_DEDICATED_ROUTE property sections (Versal and UltraScale) for all values other than false to determine the limitations for dedicated clock routing for GC pins. This becomes important, for example, if multiple clocks arrive on GC pins of a bank and they need to be routed to more clock management primitives than are available next to the I/O bank.
The clock inputs can be differential or single-ended. For single-ended clocks, the clock must be connected to P-side. The N-side cannot be used for a different clock, but can be used for general I/O. All global clock pins have access to the global clock routing (using clock primitives like buffers), which can access all clock inputs on the device. Clock I/O standards, coupling, and termination can affect the functionality of your design.
Use the following guides to help determine the best solution for your design; Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861), UltraScale Architecture SelectIO Resources User Guide (UG571), or Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). Also, the SelectIO user guides cover high-speed interfaces with clocks in their respective SelectIO Interface Logic Resources sections.
For transceiver input clocks requirements, the Board Design Guidelines section of the transceiver user guide (focus on the PCB design checklist links). Clock outputs have no restrictions on the pins they can output on.
Finally, the Zynq UltraScale+ MPSoC and Versal adaptive SoC PS clocks external connections guidelines are in the PCB guide for each device family ( UltraScale Architecture PCB Design User Guide (UG583) or Versal Adaptive SoC PCB Design User Guide (UG863)).