The Versal Adaptive SoC Design Process Hubs for AIE Engine Development collect all resources related to the design process in one easy to navigate location. Due to the revolutionary architectural change that AIE introduces, AMD strongly encourages taking the AIE training modules (select ). When beginning to design with AI Engines, the high-level process is outlined in the AI Engine System Partitioning Planning section of Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504).
For design/function tutorials, the tool used for design must be considered. If you want to use the Vitis unified software platform or the command line flow, consult the Vitis Tutorials on GitHub. If you want to start with the Vitis Model Composer, consider the Vitis Model Composer Tutorials on GitHub. Refer to the DSP Tool Flow to see the different tool flows for AIE designers.
The Vitis libraries (Documentation; Code) include a number of common algorithms that target AIE including the Vitis tools digital signal processing library. These libraries are open source and ease development time and cost.
If custom coding of the AIEs is a requirement, refer to the specific AIE kernel and graph programming guide ( AI Engine Kernel and Graph Programming Guide (UG1079), AI Engine-ML Kernel and Graph Programming Guide (UG1603)). There are also user guides for the specialized data types, intrinsics, and APIs needed to vectorize (and hopefully speed-up) generic C kernel code (AI Engine API User Guide; AI Engine Intrinsics User Guide).
To understand the AI Engine tools and flows (backend-compiler/simulators/debuggers for AIE; Host code to setup AIE), refer to AI Engine Tools and Flows User Guide (UG1076). For Vitis Model Composer AIE development, Vitis Model Composer User Guide (UG1483) is a good resource. The Vitis Unified IDE can be used to design and debug AIE application and UG1702 can be used to understand this process within the Vitis tools. Reports and waveforms from AIE compilation & simulation can be seen using the Vitis Analyzer. Finally, to integrate the AIE design with the rest of the domains to create an image that can be written to a Versal device, a platform must be used as the base for the entire design, integrated through Vitis unified software platforms, Vitis Model Composer, or command line compilers (previously mentioned).