Functional Differences - UG1192

Functional differences are a concern when changing or upgrading an IP core. Each IP I/O functional description needs to be checked against the legacy IP to ensure compatibility. Especially look for differences in polarity, handshaking, format, and latency. Review and compare timing diagrams to ensure that the cycle-to-cycle functionality is compatible, and if not, revise the logic as necessary.

Another area for attention is the block memory write mode, which can affect the clock cycle of when data is available. See the UltraScale Architecture Memory Resources User Guide (UG573) or Versal Adaptive SoC Memory Resources Architecture Manual (AM007) for more information. Also important is the input or the output registers in the IP. These are set when you customize the IP, so some tuning might be required during functional verification.

After the full RTL conversion and IP conversion is complete, functional simulation can begin. There is a Tcl export_simulation command that creates a self-contained simulation environment. For a list of options, run export_simulation -help. Use the export_simulation command for help with setting up a complete environment for the desired simulator. All scripts, libraries, and HDL files are available in this directory to make simulation and verification easy. If you prefer to simulate the IP in a stand-alone environment, example designs are provided for many IP cores. These example designs include a simulation environment. See the documentation for the specific IP block for more information about the IPs examples.