External Memory Interfaces

External Memory Interfaces - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID

UG1192

Release Date

2025-07-15

Revision

3.0.1 English

When moving external memory interfaces from Altera to AMD, there are several key architectural differences. The following table shows a comparison of the external memory interfaces for the AMD UltraScale architecture and the Altera Arria 10 architecture.

Table 1. AMD UltraScale FPGA and Altera Arria 10 FPGA External Memory Interface Comparison
Feature	AMD UltraScale FPGA	Altera Arria 10 FPGA	Notes
Recommended impedance	40 Ω	40 Ω	Some interfaces vary. See documentation for exact impedances.
On-chip termination	Digitally controlled impedance (DCI) VRP pin 240 Ω to ground	OCT 240 Ω RZQ to ground
Address and command topology	Fly-by	Fly-by
Number of independent interfaces per bank	2 Must be same voltage	1	Two independent PLLs in UltraScale/UltraScale+ allows unique frequencies, reference clocks can be shared.
Number of dependent interfaces	2 Must be same voltage	2 Must be same frequency, reference clock, voltage	Two independent PLLs in UltraScale/UltraScale+ allows unique frequencies, reference clocks can be shared.
Number of banks x16 DDR3/4	1	2	52 pins per bank fits a x16 interface in a single bank.
Clock/Address/ Command	Grouped	Fixed location based on hard controller
DDR3/4 controller	Soft block	Hard controller
DDR3/4 calibration	MicroBlaze™ processor	Hard NIOS
Debug	Vivado lab tools and XSDB debugger	Signal tap

The following table shows a comparison of the external memory interfaces for the AMD Artix 7/Spartan 7 and Zynq 7000 SoC architecture and the Altera Cyclone V and Cyclone V SoC architecture.

Table 2. AMD Artix-7/Spartan-7 FPGA and Zynq 7000 SoC and Altera Cyclone V FPGA and Cyclone V SoC FPGA External Memory Interface Comparison
Feature	AMD Artix 7 and Spartan-7		AMD Zynq 7000	Altera Cyclone V/ Cyclone V SoC FPGA	Notes
DDR3 FMAX	Artix 7: Spartan 7:	1,066 Mb/s 800 Mb/s	Up to 1,866 Mb/s	800 Mb/s
Recommended impedance	40		40	40	Some interfaces vary. See documentation for exact impedances.
On-chip termination	IN_TERM Untuned 40, 50, or 60 Ω		IN_TERM Untuned 40, 50, or 60 Ω	OCT 240 RZQ to ground to meet F_MAX untuned with lower performance	AMD no external reference pin required for untuned termination.
Address and command topology	Fly-by		Fly-by	Fly-by
Number of independent interfaces per bank	1			1
Controller	Soft			Hard for F_MAX Soft for derated
Debug	Hardware debugger			Signal Tap

Use the Vivado I/O pin planner to assign DDR memory pins. The pin planner performs on-the-fly validation of pin assignment rules for the respective I/O banks.