The following graph illustrates the development workflows for Altera Agilex SoCs and AMD Zynq™ UltraScale+™ MPSoCs. The red arrows indicate the steps where your intervention is required when migrating a design from Agilex 5 to Zynq UltraScale+ MPSoCs. The development workflow for Versal adaptive SoCs follows the same steps as Zynq UltraScale+ MPSoCs. The next table describes the activities for each step across all AMD adaptive SoCs and Altera SoC FPGAs. The final table compares the tools used for each step in both workflows.
Comparison of Altera Devices Workflow and AMD Devices Workflow
| Step | Process | AMD Flow (Versal Adaptive SoCs and Zynq UltraScale+ MPSoCs) | Altera Flow (Agilex Devices) |
|---|---|---|---|
| 1 | Create FPGA design | Create FPGA design using the AMD Vivado™ Design Suite to create the hardware design (RTL, IP cores, block design with IPI) | Use Quartus® Prime design software to design the FPGA logic (RTL, platform designer for IP integration) |
| 2 | Define processing system (PS) | Configure CIPS using Vivado tools
Specifically for Versal adaptive SoCs and after PS configuration, you can generate a basic PDI to use for design validation |
Configure hard processor system (HPS) in Quartus tools |
| 3 | Export hardware for software development | Generate and export the XSA file from the Vivado tools | Generate and export the .sopcinfo/.qsys/.xml/.sof files from Quartus tools |
| 4 | Develop software for Arm cores |
Use Vitis tools to create applications (bare metal/Linux) (or yocto flow for Linux) |
Use SoC EDS professional edition Arm Development Studio for Altera SoC FPGA Edition for software development (or yocto flow for Linux) |
| 5 | Create the complete image | Generate the complete PDI (for Versal
devices) BIN (for Zynq UltraScale+ MPSoCs) using Bootgen |
Use SoC EDS Professional Edition Arm Development Studio for Altera SoC FPGA Edition (or yocto flow for Linux) |
The following figure highlights each step in the Vivado and Vitis tools flows. It shows an example of the PDI generation process for a Versal device.
Refer to the following documents for further information.
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
- Vivado Design Suite User Guide: Design Flows Overview (UG892)
- Bootgen User Guide (UG1283)
| Stage | AMD | Altera | Purpose |
|---|---|---|---|
| FPGA hardware design | Vivado | Altera Quartus Prime | HDL design, synthesis, place & route, bitstream generation |
| System configuration and integration | Vivado IP integrator | Platform Designer (Qsys) | Block-based system design, integrating IP cores and interconnects |
| Hardware export for software | Vivado → XSA | Quartus Prime → .sopcinfo/.xml/.qsys | Hardware handoff for software tools |
| FPGA bitstream generation | Vivado (bitstream generation) | Quartus Prime (Assembler generate the .SOF file) | Generates bitstream for FPGA configuration |
| Embedded processor firmware compilation | Vitis tools (for PS/PL software development) | Altera SoC Embedded Development Suite (EDS) | Compiles software for Arm cores (Zynq UltraScale+ MPSoCsand Versal adaptive SoCs vs. Agilex SoCs) |
| Boot image packaging | Bootgen (creates PDI files) | mkimage (U-Boot), Quartus boot tools | Generates boot images for Flash or SD-cards |
| Hardware abstraction for software | Hardware-software interface (HSI) | Board support package editor (BSP) | Extracts hardware details for software development |
| Debugging and profiling | Vitis IDE, XSDB, GDB | Altera system Console, GDB, Arm DS-5 | Debugging embedded software on FPGAs and SoCs |
Looking at the previous Table 2 table, the AMD tool chain offers a simplified and streamlined workflow by requiring only two environments (Vitis tools and Vivado tools), compared to Altera's three separate tools (Quartus Prime, Arm DS, and EDS). This reduces the complexity of switching between multiple tools, enhancing efficiency and ease of use. Vivado provides a unified environment for FPGA hardware design, system integration, and bitstream generation, while Vitis tools handles embedded software development, debugging, and profiling. Additionally, Arm tools offer seamless hardware-software integration through XSA files, eliminating the need for multiple intermediate formats like .sopcinfo, .xml, or .qsys. Features like Bootgen for image packaging and HSI for hardware abstraction further enhance automation and reduce manual intervention, making the AMD tool chain more cohesive and developer friendly.
Refer to the following documents for further information.
- Altera SoC FPGA Embedded Development Suite (SoC EDS) User Guide (ID: 683187)
- Altera Quartus Prime Pro and Standard Software User Guides
- UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)
- Arm development screen for Altera SoC FPGA