AMD FPGAs and SoCs offer many roads to achieve efficient DSP designs. For designers that want to start at an algorithmic level using a higher-level programming language such as C/C++, or MATLAB® , Model Composer can be the answer. The AMD Vitis™ Model Composer tool allows the designer to construct a high-level design using blocks from the Vitis Model Composer tool (see the Vitis Model Composer User Guide (UG1483)). Additionally, the tool can be used to implement a DSP algorithm targeting Versal architecture AI Engines or programmable logic (PL).
Other paths for design entry include writing C/C++ code for Vitis tools High-Level Synthesis (see Vitis High-Level Synthesis User Guide (UG1399)), C/C++ for Versal device AI Engine design in Vitis tools and RTL in Vivado tools (see Vivado Design Suite User Guide: Design Flows Overview (UG892)). For RTL instantiation, DSPs can be instantiated through inference (multipliers through inference), the more controllable and more complex direct instantiation (DSP48E2; DSP58 types) and DSP IP (FIR Filters and Other DSP IP and Reference Designs). The following diagram shows the different design entry methods for DSP, depending on design input types.