When converting from Altera Agilex devices to AMD Versal devices (or Zynq UltraScale+ MPSoCs), several critical actions must be considered to ensure a smooth transition and compatibility across the two different SoC types. These are detailed in various sections in this document, and summarized here, complete with software steps.
Hardware Design Entry (Hardware Porting)
- Convert the HDL code (VHDL or Verilog) to be compatible with the AMD Vivado Design Suite, considering the different FPGA primitives of Altera and AMD.
- Identify the equivalent AMD IP cores in the Vivado Design Suite if there are any Altera-specific IP cores in Quartus.
- Transfer your top-level design, including the exported RTL and IP cores, to the Vivado tools environment.
- Adjust the simulation test benches accordingly to ensure proper functionality in the new design environment.
- Run design synthesis, implementation, and bitstream generation to ensure everything works as expected.
Port Drivers, Firmware, and Application
- Identify any platform-specific firmware/driver dependencies and address the differences between the Altera (HPS) and AMD (PS) SoC processing systems.
- Update the board support package (BSP) to use AMD drivers, libraries, and APIs.
- Adjust the software applications to accommodate the differences in peripherals or specific hardware features between the Agilex device and the target AMD SoC device.
Boot Process
Adapt the SoC boot process with the appropriate AMD boot firmware, bitstream, and any necessary configuration files for the target AMD SoC device. The steps mentioned previously provide general guidelines for design conversion. However, the specific actions required can vary depending on the complexity of your design.
Processing System Configuration
Processing system (PS) configuration includes identifying peripherals and configuring individual components in the system. Identifying peripherals for migration is relatively simple. First, identify the peripherals configured as a part of the current design, and then map them with the ones supported by the target AMD SoC device. The Vivado IP integrator is an advanced tool that allows easy configurability for the PS components (similar to the HPS component parameter editor in the Quartus platform designer). In addition to configuring the PS, the IP integrator presents a GUI front-end for adding IP cores on the PL side of the target AMD SoC device.
For further details see the following documents:
RTL Logic and PL Configuration
After configuring the PS block, the next step is to migrate the programmable logic part of the design. AMD SoCs include FPGA programmable logic comparable to the FPGA fabric in Agilex SoCs.
Similar to the FPGA in Agilex SoCs, the AMD SoCs PL also includes a set of integrated IP cores that can be used to implement an existing design. For example, the integrated IP cores in the Zynq UltraScale+ MPSoC PL are block RAM, DSP slice, clock management (MMCM and PLL-based), and the integrated interface block for PCI Express designs.
Additionally, the Vivado IP catalog provides soft IP cores that can be used when needed. Visit the AMD Intellectual Property website to browse IP cores and obtain more information on the IP cores supported by AMD or AMD partners. For more information, see IP Core Conversion and RTL Conversion.
Software Development
After the hardware for the PS and PL is configured using the Vivado Design Suite, the hardware design files from the Vivado Design Suite are exported to the Vitis tools or PetaLinux. The files sent from the hardware flow to the software flow (referred to as handoff or XSA files) contain information such as the hardware specification, PS peripheral information, memory map, and optionally the content for the PL.
The handoff files present the hardware design as a standard memory map, similar to any ASSP, even though the hardware could change over time. This hardware handoff file insulates software developers from the changes that might occur on the hardware side during development.
Software developers can use the handoff files to design applications, drivers, and board-support packages (BSPs). For further details, see the following documents:
Bare-metal Application
Unlike OS-based application porting, bare-metal application porting requires some effort. The bare-metal application must be modified in sync with the hardware platform and the supported address map. AMD provides bare-metal drivers (with source code) for AMD SoCs peripherals and libraries for other hardware configurations. This, coupled with BSP generation capabilities in AMD Vitis tools, simplifies the transition of a bare-metal software application to the target AMD SoC device.
The availability of source code makes it easier to modify and debug the drivers if needed. After the BSP is created, the application can be modified to make use of the target AMD SoC specific hardware components. For this migration, using a Zynq UltraScale+ MPSoC and Versal device evaluation kits with available pre-defined BSPs and application templates helps expedite the bare-metal application porting process. For further details, refer to the following documents:
Operating Systems-Based Applications
Operating system-based application migration can be easier than migrating a bare-metal application, because the operating system abstracts the lower layer from the user application and is standard across different processor systems. The migration effort can also depend on the operating system under consideration. For example, both Agilex SoCs and the Zynq UltraScale+ MPSoC support the Linux operating system while using the same Yocto project system build/environment (also applies to Versal device designs).
Consequently, migrating your application for a Linux target or supported RTOS is faster because most of the hardware differences are abstracted away at the lower levels. Refer to the following documents for further details:
Other Operating Systems
The Zynq UltraScale+ MPSoC and Versal adaptive SoCs are supported by several operating systems, including FreeRTOS, Micrium uC/OS, Android, VxWorks, and QNX. Migrating applications based on these operating systems is comparable to migrating Linux applications; however, the drivers and BSP might need to be modified for the new hardware platform. For a complete list of operating systems available for AMD SoCs, refer to the AMD Adaptive SoC Embedded Software Ecosystem (Embedded Software Ecosystem) for further information.
Boot and Configuration
Boot and configuration require some thought and probably some modification in the existing boot code. For the Zynq UltraScale+ MPSoC, one processor in the PS always boot first, allowing a software-centric approach for PL configuration. Versal devices have a dedicated boot processor that manages booting the device. The PL can be configured as part of the boot process or configured in the future.
Additionally, the PL can be completely reconfigured or used with partial dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing the PL resources by swapping in new algorithms as needed. This latter capability is analogous to the dynamic loading and unloading of software modules. The PL configuration data is referred to as a bitstream for Zynq UltraScale+ MPSoC devices or programmable definition file (PDI) for Versal devices.
Depending on the AMD device selected, a first stage bootloader (FSBL) or platform loader and manager (PLM) initializes all the necessary peripherals, and (optionally) loads the PL and application software. The processor(s) are then optionally configured to run the bare-metal application or the second stage bootloader (such as U-Boot), which then loads the chosen operating system.
See the following figures for the Zynq UltraScale+ MPSoC flow and Versal device flow.
Refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for acronyms used and the detailed explanations of the following flow.
Refer to the Versal Adaptive SoC Technical Reference Manual (AM011) for acronyms used and the detailed explanations of the following flow.
Refer to the following documents for further information: