The application processing unit (APU), real-time processing unit (RPU), connection to platform management, and CCIX to PCIe interface blocks are wrapped into a processing system IP representation called the control, interfaces, and processing system (CIPS). The CIPS IP allows you to configure the following:
- Device clocking to the PMC, PS, NoC, and optionally, PL
- PMC flash controllers, peripherals, and their associated multiplexed I/O (MIO)
- PS peripherals and their associated I/O
- PS-PL interrupts and cross-triggering
- The integrated block for PCIe with DMA and cache-coherent interconnect (CPM)
- PS and CPM AXI4 interfaces to the NoC and PL
- System Monitor supply and temperature monitoring and alarms
- High-speed debugging port (HSDP)
For more information, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
Figure 1.
Versal Architecture CIPS
Block
