The Altera SDC file uses the derive_pll_clocks constraint for deriving phase-locked loop (PLL)
generated clocks, and the derive_clock_uncertainty constraint
to propagate interclock and intraclock uncertainties. These commands do not have an equivalent
command in XDC and need to be removed. The Vivado design tools
automatically derive all generated output clocks from the mixed-mode clock managers (MMCM) and
PLL input clock objects.