User-generated Clocks
User-generated clocks in the programmable logic
(FPGA fabric) are typically divided clocks. If an Altera SDC file includes a multiply-by
option used with a value of 1, the option and the value are not needed. These examples show
the removal of the multiply_by option and the value 1.
create_generated_clock -name div_by_2_CLK -source [get_pins {div_by_2|FDIV|clk}] -divide_by 2 -multiply_by 1 -master_clock {clkdiv} [get_pins {div_by_2|FDIV|q}]create_generated_clock -name div_by_2_CLK -source [get_pins {div_by_2/FDCE/C}] -divide_by 2 -master_clock {clkdiv} [get_pins {div_by_2/FDCE/Q}]Clock Group Constraints
In the Altera SDC file, the set_clock_groups constraint needs to specify auto-derived
generated clocks from PLLs. These auto-derived clocks might have a different name in the XDC
file. To include generated clocks in the clock group constraint in the Vivado design tools, use the -include_generated_clocks option in the constraint as shown:
set_clock_groups -asynchronous -group [get_clocks {sys_clk}] -group [get_clocks {clk100 pll0|altpll_component|auto_generated|pll1|clk[0]}]set_clock_groups -asynchronous -group [get_clocks {sys_clk}] -group [get_clocks -include_generated_clocks clk100]For auto-derived clocks, you can specify the
clock name using the create_generated_clock -name <your name>
<object> command. Remaining arguments to the generated clock are
auto-derived by the tool.
Exception Constraints
Altera has a non-SDC extension for constraining delay that excludes clock skew:
set_data_delay. The equivalent for this constraint in the Vivado design tools is set_max_delay with the
-datapath_only switch.
For the exception constraints, such as false path, multicycle path, and max delay datapath
only constraints, Altera has implemented non-SDC extensions, such as
get_keepers and get_registers. These are not standard
SDC extensions and cannot be used in the Vivado design tools.
Use get_pins or get_cells instead, as shown:
Altera Constraint:
set_false_path -from [get_registers {*instance1_str:*|in_data_buffer*}] -to [get_registers {*instance2_str:*|out_data_buffer*}]set_false_path -to [get_keepers {*std_synchronizer:*|din_s1}]set_false_path -from [get_cells -hier -filter {name == top/instance1/in_data_buffer && ref_name =~ FD*}] -to [get_cells -hier -filter {name == top/instance2/out_data_buffer && ref_name =~ FD*}set_false_path -to [get_pins {top/modA/std_synchronizer/inst1/Q} ]Set/Report Max Skew
The Quartus constraint to constrain the bits within a bus set_max_skew is
the equivalent of set_bus_skew in the Vivado tools.
Reporting of bus skew can be done using report_bus_skew, which is the same
as the Quartus report_max_skew command.
Validating Timing Constraints
After you have converted your constraints, load your design and constraints into the Vivado tool. Make sure to review all messages you get while loading the constraints. Finally, run these commands to confirm that the constraints are correct and complete:
-
report_methodology -name methodology -file methodology.rpt- This is the detailed methodology violations report.
- It is important to run this before
report_timing_summary. - AMD recommends reviewing and resolving any critical warning. Critical warnings are issues that pose severe performance or functional danger.
-
report_timing_summary -name timing -file timing.rpt- Review the check timing and methodology summary section.
-
AMD recommends resolving any item listed here with the exception of
missing I/O constraints.
-
write_xdc -force -constraints invalid <file name> - List all constraints that are invalid and that needs to be either removed or corrected.
-
The Timing Constraints Wizard is a powerful tool designed to identify and manage missing timing constraints. It analyzes the netlist, clock nets connectivity, and existing timing constraints to provide recommendations based on the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949). The wizard covers three primary categories of constraints: clocks, input and output ports, and clock domain crossing. You can accept or modify the recommended constraints, but caution is advised as unchecking constraints early in the wizard can prevent the identification of other missing constraints. The wizard does not recommend constraints that introduce unsafe timing analysis and does not fix incorrect constraints that were already present. For more information on the timing constraints wizard, see the Vivado Design Suite User Guide: Using Constraints (UG903).
Other documents to reference:
- For more information on the Tcl commands in the Vivado Design Suite, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
- Details on check timing and the methodology report warnings are in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
- Detailed information of all timing constraints is documented in Vivado Design Suite User Guide: Using Constraints (UG903).