Other than adopting to the Vivado hierarchical cell, net or pin naming, the
constraints for primary clocks with the create_clock constraint do not need
any change. The input and output delay constraints also do not need to change if the board
design has not changed. If the board delay has changed, then the maximum and minimum values
must be adapted to reflect the new board design.
In theory, specific user clock uncertainty constraints with the set_clock_uncertainty constraint can remain as-is. However, AMD recommends a review of the need to add additional margin when
migrating a design. The device speed files in the Vivado Design Suite include sufficient margin to guarantee functionality across
process, voltage, and temperature (PVT).