AMD UltraScale, UltraScale+, and Versal devices create ASIC-like clocking with regional and segmented clock structures and flexible clock placement to maximize performance margin and reduce dynamic power. This is accomplished with multi-purpose clock I/O pins, clock buffers, clock routing, and clock frequency synthesis, deskew, and jitter filtering resources. The UltraScale Architecture Clocking Resources User Guide (UG572) provides an explanation of the resources available in the UltraScale and UltraScale+devices. The same type of information is also available for Versal devices ( Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)). There are many guidelines for creating efficient clock networks. Many are combined into UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) for UltraScale and UltraScale+ designs and Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387) for the Versal architecture. Also, there are guidelines for transceivers clocks in each transceiver user guides by device family. Finally, there are extra guidelines for clocking for the processing systems (PS) pin connections (Zynq UltraScale+ MPSoC and Versal adaptive SoCs).
Note: In the clock sections, the term UltraScale device is used to refer to both
the UltraScale and UltraScale+
families, because they share a common clocking architecture.