Clocking visualization can be done in the Vivado Design Suite. The Advanced Vivado Tools Tips and Tricks section describes how to visualize clock primitives, clock net routing, and clock sites.
- Clocking problems in designs include failure to place and route, long compile times, and negative timing slack. To find out if non-optimal clock architectures or resources are used in the design, consider using report_drc and report_methodology Tcl commands. See Vivado Design Suite Tcl Command Reference Guide (UG835).
- There are clocking specific design rules (report_drc) and methodology checks (report_methodology).
- For a high-level look at clock resource utilization in the design, use the report_utilization Tcl command and look at the Clock Resources section in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
- To understand the clock resources used, especially regarding clock routing and which clock regions have loads, you can use report_clock_utilization.
- An article on resolving clock partitioning failures is available with information on clock errors in implementation.
- Timing closure and the impact of clocking are discussed in the Design Closure section of the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).
All these commands can be run in the GUI from the report pull-down menu on a synthesized or implemented design or through the Tcl console.