There are extensive recommendations for clocking RTL best practices in the Clocking Guidelines section of the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949). The following list highlights some general suggestions in the user guide and the recommended best practices.
- Avoid gated clocks. Use clock enables on global clock buffers.
- Keep clocking components at the top RTL level.
- Keep clocking on dedicated global clocking routing using dedicated clock pins and clock resources (example, global clock buffers), instead of using local routing.
- Avoid using cascaded clock buffers. They are not recommended.
- Use parallel clock buffers when two related clocks are needed to ensure predictable placement and matched insertion delay.
- Use clock division in global buffers (BUFG_GT, MBUFG*, BUFGCE_DIV) to reduce the need for more complex, power intensive clock primitives (example, MMCM) when no other features of these clock primitives are needed (example, clock jitter reduction in MMCM).