There are multiple properties to help guide placement and routing of clock resources. See UG949 for UltraScale devices and UG1387 for Versal devices. One of the more common clock properties is the CLOCK_DELAY_GROUP that is used on the nets of clocks for synchronous domains. Use this property on clocks with the same MMCM, PLL, GT source, or common driver to be balanced during placement and routing to reduce clock skew on timing paths between the clocks. This property can be setup if using the clocking wizard through the Matched Routing checkbox and Clock Grouping pull-down for Versal devices. There are other properties to consider for advanced use cases or if the default placement and routing lead to errors or timing violations. For Versal devices, there is the USER_CLOCK_VTREE_TYPE property (definition; usage) that can be applied to clock nets, instead of GCLK_DESKEW, which is not mentioned in the references provided.