Clock Management Types

Clock Management Types - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID

UG1192

Release Date

2025-07-15

Revision

3.0.1 English

Multiple clock functions are listed in the following table. They are used to generate clocking for specific and general purpose tasks on UltraScale and Versal devices.

Table 1. Clock Management Types
Type	Description	Device Family/Series	Input(s)/Output(s)	Use Cases/Features
MMCM	Mixed-mode clock manager	UltraScale, Versal	2/7	Frequency synthesis (includes fractional divide) Spread spectrum removal on input clock Spread spectrum output clock generation Clock network deskew Jitter filter Zero delay buffer Cascade to MMCM/DPLL (Versal devices only)
PLL	PLL (used for I/O and programmable logic)	UltraScale	1/2	Frequency synthesis Spread spectrum removal on input clock Spread spectrum output clock generation Clock network deskew Jitter filter Zero delay buffer
DPLL	Digital PLL for low frequency clocks	Versal	1/4	Frequency synthesis (no duty cycle programmability) Clock network deskew Jitter filter Zero delay buffer Cascade to MMCM/DPLL
XPLL	High-performance PLL (used for I/O and programmable logic; renamed PLL from UltraScale families)	Versal	1/4	Frequency synthesis Clock network deskew Jitter filter XPLL to XPLL cascade
All clock management types allow dynamic reconfiguration. Transceiver PLLs are specified in the device specific transceiver user guide. See documents listed in the PC Board Design Guidelines section.