In the UltraScale clock architecture, GC pins can be connected to clock buffers, MMCMs, and PLLs that are in a clock management tile (CMT) adjacent to the same I/O bank as the GC pins. HDIO banks do not exist in the UltraScale family. In the UltraScale+ family, HDIO bank GC pins (HDGC) do not have an adjacent CMT and can only drive BUFGCEs (no MMCM/PLL) through non-dedicated clock routing, which is not as good as dedicated clock routing. If an HDGC pin needs to be connected to an MMCM or PLL, then it first must be connected to a BUFGCE. The input net from the pin needs to have the CLOCK_DEDICATED_ROUTE property on it set to False.
For Versal adaptive SoCs, GC pins can be connected to clock buffers, MMCMs, DPLLs, and XPLLs that are next to the I/O bank. For HDGC pins, there are four BUFGCE, along with a DPLL that can be connected through dedicated clock routing. If the HDGC pin needs to be connected to an MMCM or XPLL, then it first must be connected to a BUFGCE through dedicated clock routing. The HDGC pins can connect directly to the DPLL next to the I/O bank with he HDGC pins.
For both UltraScale and Versal devices, there are recommended clocking topologies when using multiple BUFGCE/BUFGCTRL/BUFGCE_DIV that create clock domains that interact. See Clocking Topology Recommendations in UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) or Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).