Clock buffers allow local clocks, clocks from the PS, transceiver clocks, and clocks from I/O to reach the global clock routing network. The following table shows the different clock buffers used by the UltraScale and Versal devices. There are a subset of buffers in hardware (see the hardware buffer column) that can then create a larger selection of buffers to instantiate in RTL.
| Buffer Type | Description | Hardware Buffer | Device Family/Series |
|---|---|---|---|
| BUFG | Simple clock buffer | BUFGCE | UltraScale, Versal |
| BUFGCE | Clock buffer with enable | BUFGCE | UltraScale, Versal |
| BUFGCE_DIV | Clock buffer with enable and divider {1..8} | BUFGCE_DIV | UltraScale, Versal |
| BUFGMUX/BUFGCTRL | Two clock multiplexer | BUFGCTRL | UltraScale, Versal |
| BUFG_GT | Clock buffer driven by transceiver | BUFG_GT | UltraScale, Versal |
| BUFG_FABRIC | Buffer for high fanout signal nets | BUFG_FABRIC | Versal |
| BUFG_PS | Clock buffer for PS clocks | BUFG_PS | UltraScale, Versal |
| MBUFGCE | Multiple output clock buffer with dividers {1,2,4,8} | BUFGCE | Versal |
| MBUFGCE_DIV | Clock buffer with enable and two separate cascaded dividers of {1..8} and {1,2,4,8} | BUFGCE_DIV | Versal |
| MBUFGMUX/MBUFGCTRL | Two clock multiplexer with dividers {1,2,4,8} | BUFGCTRL | Versal |
| MBUFG_GT | Clock buffer driven by transceiver with dividers {1,2,4,8} | BUFG_GT | Versal |
| MBUFG_PS | Clock buffer for PS clocks with dividers {1,2,4,8} | BUFG_PS | Versal |