Note: This is not a complete reference for the available Tcl commands.
| Command | Description |
|---|---|
| GUI Commands | |
| start_gui | Opens the Vivado IDE with the current design in memory. |
|
stop_gui |
Closes the Vivado IDE with the current design in memory. |
| Adding Design Sources | |
| read_verilog | Reads Verilog (.v) and System Verilog (.sv) source files |
| read_vhdl | Reads the VHDL (.vhd or .vhdl) source files. |
| read_edif | Reads an EDIF netlist file into the design source fileset of the current project. |
| read_ip | Reads existing IP (.xci) project files. |
| read_xdc | Reads .sdc or .xdc format constraints source. |
| read_bd | Reads existing IP integrator block designs (.bd) |
| read_checkpoint | Reads a design checkpoint (.dcp) into the in-memory design. |
| Compilation | |
|
link_design |
Loads a synthesized design. |
| synth_design | Synthesizes the design. |
| opt_design | Performs high-level design optimization. |
| power_opt_design | Performs intelligent clock gating to reduce overall system power (optional). |
| place_design | Places the design. |
| phys_opt_design |
Performs physical logic optimization to improve timing or routeability (optional). |
| route_design | Routes the design. |
| Analysis 1 | |
| report_timing_summary | Generate a timing summary to help understand if the design has met timing requirements. |
| report_methodology | Runs a specified set of methodology checks, reporting any errors or violations. |
| report_design_analysis | Provides timing data on critical path characteristics and complexity of the design to help identify and analyze problem areas that are subject to timing closure issues and routing congestion. |
| report_qor_suggestions | Report design and tool option recommendations related to improving the quality of results (QoR). |
| report_qor_assessment | Checks for potential issues in the design and evaluates the likelihood of meeting design goals. |
| report_drc | Runs design rule checks. |
| Data Management | |
| set_property | Assign a property value to a design object. |
| write_bitstream | Generates a bitstream file and runs DRCs. |
| open_checkpoint | Load a design checkpoint (DCP) which is snapshot containing the netlist, constraints, and physical data. |
| write_checkpoint | Saves the design (DCP file) at any point in the flow. |
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