Attributes, also known as directives in Quartus are typically called properties in Vivado tools. Vivado tools also uses the term directives, but as switch to set the optimization modes of the various stages of the synthesis and implementation flow. To avoid confusion, the term attribute is used in this section.
AMD recommends the following flow to convert directives:
- Analyze and identify all directives. Directives can be
identified using:
"find in files" for "(*" (verilog) or "attribute" (VHDL) - Create a table of attributes with their name and location.
- Find the equivalent attributes using the following table.
- Modify the HDL source code.
Note:
Vivado synthesis
does not report unsupported attributes. If the specified attribute is not recognized by the
tool, Vivado synthesis passes the attribute and its value to
the generated netlist.
The following table lists the Quartus Prime directives and their equivalent in the Vivado Design Suite.
| Quartus Prime Attribute | Equivalent Vivado Attribute 1 | Description |
|---|---|---|
| altera_attribute | Use XDC or Tcl | Make assignments to objects |
| chip_pin | PACKAGE_PIN | Assign device pins to a port |
| direct_enable | DIRECT_ENABLE | Force signal as enable of flop |
| dont_replicate | DONT_TOUCH | Prevent register replication |
| dont_retime | DONT_TOUCH | Prevent re-timing |
| dont_merge | KEEP/DONT_TOUCH 2 | Prevent register merging |
| enum_encoding (VHDL) | fsm_encoding | Specify FSM enumeration type |
| full_case (verilog) | full_case (verilog) | Indicate that all possible case values are specified |
| keep | KEEP | Prevent synthesis optimizations |
| library | Use project settings or set_property library <lib> [get_files] | Set destination library for design unit |
| max_depth | Not supported | Specify maximum depth of inferred memory blocks |
| maxfan | FORCE_MAX_FANOUT | Drive replication to respect maximum fanout |
| multistyle | USE_DSP | Multiplier style |
| noprune | DONT_TOUCH | Prevent floating logic optimization |
| parallel_case | (* parallel_case *) | Build case statement as parallel structure |
| preserve | DONT_TOUCH | Prevent redundant or constant driver optimization |
| ram_init_file | See Specifying RAM Initial Contents in an External Data File in Vivado Design Suite User Guide: Synthesis (UG901) | Specify initial content of memory |
| ramstyle | RAM_STYLE | Specify type of inferred RAM |
| read_comments_as_HDL | Not supported | Perform synthesis on portions code in comments |
| romstyle | ROM_STYLE | Specify type of inferred ROM |
| syn_encoding (verilog) | FSM_ENCODING | Specify FSM enumeration type |
| synthesis translate_off | SYNTHESIS TRANSLATE_OFF | Synthesis ignore portion of code |
| synthesis translate_on | SYNTHESIS TRANSLATE_ON | Synthesis enable again |
| useioff | IOB | Implement I/O connected registers in I/O block |
| verilog_input_version | Use HDL file property in Vivado project | Specify verilog version (VERILOG_1995, VERILOG_2001, or SYSTEMVERILOG_2005) |
| vhdl_input_version | Use HDL file property in Vivado project | Specify VHDL version (VHDL_1987, VHDL_1993, or VHDL_2008) |
|
||