Use the following steps to convert an
Altera clock architecture to an AMD clock architecture.
Figure 1. Altera to AMD Clock Conversion
Process
- Board design and pin selection: Choose clock capable I/O pins for the clocks
coming into the AMD device (included in the Global Clock Inputs and Board Planning section).
Optionally: Prototyping clock networks is a good way to validate the structure (included in Prototyping Clock Networks section).
- Build the clock network:
- Choose AMD MMCM/PLL/DPLL/XPLLs (included in Clock Management Types) to replace Altera PLLs. There are two methods (included in Recommended Design Clock Insertion Method section). The performance of the clock buffers, clock network, and clock management tiles can affect the resources chosen. The links are provided in the Maximum Performance section to guide resource selection based on performance. Clock buffers can also be instantiated through the clock wizard depending on the options chosen. When adding in clocks, manage the types of buffers, and consider the Clocking RTL Best Practices section.
- Choose AMD clock buffers to add into the design of global clock signals (included in Clock Buffer Types). Some of these might already be instantiated through the clock wizard. Only include cascaded clock buffers that are needed. This also includes removing ALTCLKCTRL IP and replacing the functionality already existing on the AMD clock buffers. Finally, if there are any gated clocks in the design, remove them and replace with clock enables on clock buffers.
- Implementation and debug: Implement design, visualize, create reports, and debug any problems as described in the Clocking Visualization, Report Generation, and Debug section. Use the Clock Constraints section to help guide routing if the default clock settings do not meet timing requirements or result in clocking errors.
To further your understanding of UltraScale and Versal device clocking, refer to the Clock Routing section included in the Clock Resources Location sections.