Analysis
AMD recommends creating a list to prepare for the conversion of Altera Quartus IP cores. At minimum, this IP list needs to contain:
- IP type
- Hierarchical name
- HDL file name that instantiates the IP
- IP core parameters (if parameterizable IPs are part of your design)
Most of the required information is provided in the Analysis and Synthesis section of the Quartus Prime project compilation report window. Consult these report sections (when present) to collect data:
- RAM summary
- DSP block usage summary
- IP cores summary
- LPM parameter settings
- PLLs
- RAMs
- Multipliers
This information is also available in the map report (.map.rpt) in the Parameter Settings by Entity Instance section.
The Quartus Prime report table contents can be
copied and pasted or directly exported to a CSV file for importing to a spreadsheet. To
export to a CSV file, right-click the file, select export and select CSV
format from the drop-down list.
From the previous analysis, it can be determined whether the original IP cores are static or parameterizable configurations. A static IP core configuration produces the identical IP core configuration each time it is instanced in a design. A parameterizable IP core configuration is given unique parameters for each instantiation. Consequently, each instanced parameterizable IP core is unique. The available parameters vary per IP core type.
Some examples of these parameters are port data width, pipelining depth, and memory/FIFO depth. The subsequent sections in this chapter outline the conversion steps for static and parameterizable IP cores.
A column for effort estimate can be added to the IP core conversion list. When estimating the task effort, consider all aspects of the design conversion process:
- IP generation
- Adaptation of the interfaces and signals in the HDL code
- Verification of the synthesis and implementation results
- Simulation and hardware verification