While porting your design into the AMD Vivado™ Design Suite, here are some useful advanced tool features and processes to help with the design entry and debug process.
Finding and Marking Objects in the Vivado Design Suite
This can apply to many different objects including:
- Clocks
- Transceivers
- Block RAM and UltraRAM sites
- Netlist objects such as Cells, Nets, and Pins
The following process is used to find FPGA resources in a synthesized or implemented design.
- Opening Designs
-
Find FPGA Primitives used in design
with the following fields:
- Find: Cells
- Properties: PRIMITIVE_TYPE is what primitive type that is used that you are searching for (for example, CLOCK or BUFFER)
- A few optional next steps:
- Click on an item in the Find Results window and look at the cell properties. See Vivado Design Suite Properties Reference Guide (UG912) for property definitions.
- Mark or highlight the FPGA primitives used to see connections in the Schematic window or placement in the Device window, after implementation for it to show up in the Device View.
- Right-click on one or more items and select Schematic. Then look at the Schematic window. This shows the connections of resources without caring about placement. Expand logic from selected cells to see the list of clock, reset, datapath enable connections available.
- Click on a pin of a clock resources in the Schematic or Device view. Then right click on the Net name and click Net properties. Net properties for a clock can contain interesting information like what the net is connected to (connectivity tab), along with properties like USER_CLOCK_VTREE_TYPE (in the properties tab; Versal device clock properties only). Also, in the device view when a net is selected after implementation, the fanout can show all the connections of the clock net.
- After implementation, click on a net in a schematic window. Go to the Device Window to see where all the connections of that net are physically.
- Specifying Schematic Window Settings.
- Setup Slack for * Pins options can help with timing analysis (after running a Report Timing Summary).
- The Show Hierarchy and Autohide pins *
options can help create more viewable schematics. Also, right click on the
cell/net/hierarchical pin and select Remove Selected Items to
Schematic to removed unneeded elements in schematic view.
- For understanding timing in schematics, right click on primitive pin/net/cell in a schematic and click on an option in Report Timing to generate a helpful timing report.
- Find all potential FPGA resources available (including unused) on the device.
- Open a design
-
Find Clock Objects
- Find: Sites
- Properties: SITE_TYPE is <FPGA Resource>
- <FPGA Resource> can be for a clocking example MMCM or BUFGCE.
- A few optional next steps:
- Mark or Highlight Sites
- Click on an item in the Find Results window and look at the site properties (See Vivado Design Suite Properties Reference Guide (UG912) for property definitions).