AXI and Avalon Differences - UG1192

AMD uses the industry standard AMBA® AXI interface protocol, while Altera uses the proprietary Avalon interface protocol. One possibility for interfacing existing Avalon-based interfaces with AXI4 is inserting a logic shim module to translate the interface handshaking and buffer the data. However, this approach requires adding FIFOs, which increase latency and consume resources. Further, the complexity of designing the shim logic is about equal to the effort in redesigning the existing interface, because in either case the user designs the interface to the AXI4 standard.

There is a memory-mapped and streaming interface for both AXI and Avalon. For the streaming interface, it is virtually a 1:1 mapping. Avalon has a start of packet signal (SOP), as shown in the following table.

AXI indicates SOP with the assertion of TVALID and TREADY at the same time. Looking at a 10G MAC IP core for example (see the following figures), it is easy to see the similarity in the interface timing waveforms.

However, there are some subtle differences, as listed in the following table.

For the memory-mapped version, AXI separates the data, address, and control into different channels. The user logic for an Avalon interface requires some minor modifications for adaptation to the AXI standard. For example, the logic that generates an address value must also generate a valid signal with it as long as ready is asserted.

The following figure shows an example of an AXI memory-mapped interface. One channel is the address and another is the read data. Burst count is controlled by the AWLEN port, which is not shown.

Avalon has a single channel for data, address, and control, as shown in the following figure.

Inspection of these timing diagrams shows that the two main differences between the interface protocols are the channels, and the lack of back-pressure with the Avalon interface. Avalon has a waitrequest signal, but this is a slave to a master only, and the master cannot throttle data. AXI separates writes and reads into different channels and the master or slave can throttle data as required. See the applicable IP core user guide on the AMD documentation website for detailed port configurations. After the differences between the Avalon and AXI interfaces are understood, it is possible to modify the existing user logic to be compliant with the AXI interface. For more information about the AXI interface, see the Vivado Design Suite: AXI Reference Guide (UG1037). Additional information can also be found on the AMBA AXI4 Interface Protocol page.