Vector Registers - Vector Registers - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

Vector registers are wide to allow SIMD instructions and to be used as operand storage. These registers are prefixed with a W. There are 24 x 256-bit registers: wln and whn, n = 0..11. Two W registers can be grouped to form a 512-bit register prefixed with an X. Two X registers then can be grouped to form a 1024-bit register with the prefix Y.

Table 1. AIE-ML v2 Vector Registers
256-bit 512-bit 1024-bit
wl0 x0 y0
wh0
wl1 x1
wh1
wl2 x2 y1
wh2
wl3 x3
wh3
wl4 x4 y2
wh4
wl5 x5
wh5
wl6 x6 y3
wh6
wl7 x7
wh7
wl8 x8 y4
wh8
wl9 x9
wh9
wl10 x10 y5
wh10
wl11 x11
wh11