| dn0..dn7 |
20 bits |
AGU dimension size register |
| dj0..dj7 |
20 bits |
AGU dimension stride (jump) register |
| dc0..dc7 |
20 bits |
AGU dimension count register |
| s0..s3 |
6 bits |
Shift control |
| sp |
20 bits |
Stack pointer |
| lr |
20 bits |
Link register |
| pc |
20 bits |
Program counter |
| fc |
20 bits |
Fetch counter |
| |
32 bits |
Status register
1
|
| |
32 bits |
Mode control register
1
|
| ls |
20 bits |
Loop start |
| le |
20 bits |
Loop end |
| lc |
32 bits |
Loop count |
| lci |
32 bits |
Loop count (PCU) |
| F |
128 bits |
MX6 data MSB registers |
| G |
64 bits |
MX6 sub-title shift registers |
| E |
64 bits |
MX6 exponent registers |
- The status and control
registers are each separate registers of a small number of bits
each. Only through the debug interface are the various
individual registers accessed together as one 32-bit wide SR and
CR register.
|