Scalar Registers - Scalar Registers - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

Scalar registers include configuration registers. See the following table for register descriptions.

Table 1. Scalar Registers
Syntax Number of bits Description
r0..r31 32 bits General-purpose registers
m0..m7 20 bits Modifier registers
p0..p7 20 bits Pointer registers