The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/23/2025 Version 1.1 | |
| Performance | Added a section and table. |
| AIE-ML v2 Tile Architecture | Updated the section. |
| Memory-mapped AXI4 Interconnect | Updated the section. |
| AXI4-Stream Interconnect | Updated the section. |
| AIE-ML v2 Memory Module | Updated the Tile DMA Controller bullet. |
| Trace | Updated the section. |
| AIE-ML v2 Array Interface | Updated the first table note. |
| Functional Overview | Updated sparsity bullet in the Vector Multiplication Unit section. |
| AIE-ML v2 Memory Tile Overview and Features | Updated the first paragraph. |
| Comparison of AIE Generations | Updated the AIE-ML v2 entry for Bandwidth to Local Memory: Load from data memory in neighboring Tiles. |
| 07/24/2025 Version 1.0.2 | |
| General updates | Editorial updates only. No technical content updates. |
| 06/11/2025 Version 1.0.1 | |
| Introduction to Versal Adaptive SoCs | Updated the section. |
| 05/30/2025 Version 1.0 | |
| Initial release. | N/A |