Privileged Register Access Control - Privileged Register Access Control - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

AIE-ML v2 has a few privileged registers. These registers exist in the AIE-ML v2 tile, memory, and array interface-tiles. The security mechanism controls write requests to these registers and has no effect on reads to these registers. Per the AXI4 protocol, an AXI4 write transaction with AWPROT[1]=0 indicates that the transaction is secure. AIE-ML v2 allows secure transactions to write to privileged registers in the array-interface tile registers. It also allows an external privileged manager to have secured write transactions.