The AIE-ML v2 array has a single
clock domain for all the tiles and array interface blocks. The performance targed of
the AIE-ML v2 array for the –1 speed
grade devices is 1 GHz with VCC_AIE at 0.725V. In addition, the AIE-ML v2 array has clocks for interfacing to
other blocks. The following table summarizes the various clocks in the AIE-ML v2 array and their performance
targets.
| Clock | Target for –1L | Source | Relation to AIE-ML v2 Clock |
|---|---|---|---|
| AIE-ML v2 array clock | 1 GHz | AIE-ML v2 PLL | N/A |
| NoC clock | 1000 MHz | NoC clocking | Asynchronous, clock domain crossing (CDC) within the NoC |
| PL clocks | 500 MHz | PL clocking | Asynchronous, CDC within AIE-ML v2 array interface |
| NPI clock | 300 MHz | NPI clocking | Asynchronous |
The following table shows the minimum bandwidth of the AXI4 memory-mapped interface by target block, under the following conditions:
- The AXI4 memory-mapped manager operates ideally.
- Access occurs in bulk and contiguously.
- Bandwidth measures at the AIE-ML v2 array AXI4 NoC subordinate interface (NSU).
- AIE-ML v2 array clock runs at 1 GHz.
The actual bandwidth varies depending on:
- Internal bottlenecks and other non-idealities of the AXI4 memory-mapped manager (for example, PS, DMA in PMC, custom AXI4 manager in PL).
- Contention in the NoC.
- The AXI4 memory-mapped burst size and data access pattern.
- The AIE-ML v2 array clock frequency.
| 128-bit Access | 32-bit Access | |||
|---|---|---|---|---|
| Block | Target Write BW (GB/s) | Target Write BW (GB/s) | Target Write BW (GB/s) | Target Write BW (GB/s) |
| Tile and memory tile data memory | 3.0 | 1.1 | 0.80 | 0.32 |
| Tile program memory | 2.9 | 1.1 | 0.32 | 0.32 |
| Tile, memory tile, and array interface tile stream-switch and BD registers | 3.0 | 2.0 | 1.7 | 0.80 |