Overview - Overview - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document_ID: AM027
Release_Date: 2025-10-23
Revision: 1.1 English

Overview
Introduction to Versal Adaptive SoCs
Navigating Content by Design Process
Introduction to AI Engines and AIE-ML v2
AIE-ML v2 Array Features
AIE-ML v2 Tile Features
AIE-ML v2 Memory Tile Features
AIE-ML v2 Array Interface to NoC and PL Resources
AIE-ML v2 Array Overview
AIE-ML v2 Array Hierarchy
Performance
Clocking Structure
Memory Error Handling
Privileged Register Access Control
AIE-ML v2 Tile Architecture
Memory-mapped AXI4 Interconnect
AXI4-Stream Interconnect
AIE-ML v2 Tile Program Memory
AIE-ML v2 Interfaces
AIE-ML v2 Memory Module
AIE-ML v2 Debug
AIE-ML v2 Trace and Profiling
Trace
Profiling (Performance Counters)
AIE-ML v2 Events
AIE-ML v2 Array Interface Architecture
AIE-ML v2 Array Interface
Interrupt Handling
AIE-ML v2 Architecture
Functional Overview
Register Files
Scalar Registers
Special Registers
Vector Registers
Mask Registers
Accumulator Registers
Instruction Fetch and Decode Unit
Load and Store Unit
Scalar Unit
Arithmetic Logic Unit and Scalar Functions
Vector Unit
Fixed-point Vector Unit
Fixed-Point SRS and UPS Conversions
Floating-point Vector Unit
Register Move Functionality
AIE-ML v2 Memory Tile Overview and Features
AIE-ML v2 Memory Tile Memory
AIE-ML v2 Memory Tile DMA
AIE-ML v2 Memory Tile Locks Module and Stream Switch
AIE-ML v2 Configuration and Boot
AIE-ML v2 Array Configuration
AIE-ML v2 Boot Sequence
AIE-ML v2 Array Reconfiguration
Comparison of AIE Generations
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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