This is the data path for integer vector data. The multiplication data path is split into six pipeline stages as shown in the following diagram.
The features of the units in the multiplication datapath are as follows:
- There are two permute units that handle a set of permutes of X vector registers.
- The multiplier unit is fed by the output of the permute blocks.
- The post-add and accumulate unit adds the result of the multipliers with up to two accumulator inputs.
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- 16 lanes of 32-bit
- 32 lanes of 16-bit
- 64 lanes of 8-bit
In addition to the multiplier datapath, there are two additional vector units: shuffle/shift and add/compare. The input comes directly from two vector registers and the results are stored back in the vector registers.
The vector add/compare units support the following bit-width modes (both signed and unsigned):
- 16 lanes of 32-bit
- 32 lanes of 16-bit
- 64 lanes of 8-bit
The vector add/compare unit supports lane-by-lane control whether addition or subtraction is performed. This unit also has limited support for 16-bit and 8-bit floating point formats. This includes the following modes in a lane-by-lane fashion:
- x < y, x > y, x ≤ y, x ≥ y, x < 0
- min(x,y), max(x,y)
The vector shift unit takes one or two 512-bit vector registers as an input and produces one 512-bit output vector. It supports the following modes:
- Standard right shift with 8-bit granularity
- Shift and push in scalar value either at the left or right-hand side. An 8, 16, or 32-bit lane can be shifted into the LSB lane of a 512-bit vector register, and all existing values are shifted one lane up. The value of MSB lane is dropped.
The shuffle unit allows different modes to transform the input vectors. It supports the following features:
- Interleaving and de-interleaving of values at 8-bit, 16-bit, and 32-bit
- Extraction of upper and lower half of the transformed input.
- The shuffle unit shuffles the exponents and sub-tile shifts from MX block floating-point data.