A block diagram of the units is shown in the following figure.
Figure 1. Fixed-point SRS and UPS Datapath
The SRS unit reads an accumulator register, performs the conversion, and restores the result either back to the vector register or directly to memory. The UPS unit reads a vector register directly from memory or a register and stores the result into an accumulator register. The supported modes include:
- 8-bit to/from 32-bit conversion
- 16-bit to/from 32-bit conversion
- 16-bit to/from 64-bit conversion
- 32-bit to/from 64-bit conversion
The core supports a floating-point conversion mode which converts bfloat16/float16/bfloat8/float8 to a single precision or the other way around. The following modes are supported:
- Floating-point to floating-point conversions:
- 16/32 lanes of fp32 accumulators to bfloat16/float16 vector registers
- 16/32 lanes of bfloat16/float16 vector registers to fp32 accumulators
- 32 lanes of fp32 accumulators to bfloat8/float8 vector registers
- Floating-point to integer conversions: 16 lanes of bfloat16 vector registers to 32-bit signed integers
- Block Floating-point to floating-point conversions:
- A block of MX9 data converts to single precision floating-point accumulators
- A block of MX6 data converts to single precision floating-point accumulators
- A block of MX4 data converts to single precision floating-point accumulators
- Floating-point to MX conversions:
- A block of single precision floating-point accumulators converts to a block of MX9 with 16 8-bit mantissas with a shared exponent and sub-tile shift values.
- A block of single precision floating-point accumulators converts to a block of MX6 with 16 5-bit mantissas with a shared exponent and sub-tile shift values.
- A block of single precision floating-point accumulators converts to a block of MX4 with 16 3-bit mantissas, a shared exponent and sub-tile shift values.