Comparison of AIE Generations - Comparison of AIE Generations

Table 1. Comparison of AIE Generations
	AI Engine	AIE-ML	AIE-ML v2
Compute
Multipliers per Tile (non-exhaustive list)	128 (INT8xINT8) 8 (fp32)	256 (INT8xINT8) 128 (bfloat16)	512 (INT8xINT8) 256 (bfloat16, fp16) 512 (fp8) 512 (MX9) 1024 (MX6)
Bandwidth to Local Memory
Load from data memory in same Tile	64 B/cycle	64 B/cycle	128 B/cycle
Load from data memory in neighboring Tiles	64 B/cycle	64 B/cycle	64 B/cycle from a single neighbor 128 B/cycle from two neighbors
Store	32 B/cycle	32 B/cycle	64 B/cycle
Cascade bandwidth	48 B/cycle	64 B/cycle	64 B/cycle
On-chip Data Memory
Per Compute Tile	32 KB 128 B/cycle (8 x 16B banks)	64 KB 128 B/cycle (8 x 16B banks)	64 KB 256 B/cycle (8 x 32B banks)
Per Memory Tile	No memory tiles	512 KB 256 B/cycle (16 x 16B banks)	512 KB 256 B/cycle (16 x 32B banks)
DMAs
Compute Tile	2 MM2S 2 S2MM	2 MM2S 2 S2MM	2 MM2S 2 S2MM
Memory Tile	No memory tiles	6 MM2S 6 S2MM	6 MM2S 6 S2MM
Interface Tile	2 MM2S 2 S2MM	2 MM2S 2 S2MM	2 MM2S 2 S2MM
Stream Interconnect
	32b	32b	64b
Compute Tile	South to North: 6 (24 B/cycle) North to South: 4 (16 B/cycle) East to West: 4 (16 B/cycle) West to East: 4 (16 B/cycle)	South to North: 6 (24 B/cycle) North to South: 4 (16 B/cycle) East to West: 4 (16 B/cycle) West to East: 4 (16 B/cycle)	South to North: 6 (48 B/cycle) North to South: 4 (32 B/cycle) East to West: 4 (32 B/cycle) West to East: 4 (32 B/cycle)
Memory Tile	No memory tiles	South to North: 6 (24 B/cycle) North to South: 4 (16 B/cycle) East to West: 0 West to East: 0	South to North: 6 (48 B/cycle) North to South: 4 (32 B/cycle) East to West: 0 West to East: 0
Interface Tile	From South: 8 (32 B/cycle) To South: 6 (24 B/cycle) From North: 4 (16 B/cycle) To North: 6 (24 B/cycle) East to West: 4 (16 B/cycle) West to East: 4 (16 B/cycle)	From South: 8 (32 B/cycle) To South: 6 (24 B/cycle) From North: 4 (16 B/cycle) To North: 6 (24 B/cycle) East to West: 4 (16 B/cycle) West to East: 4 (16 B/cycle)	From South: 8 (64 B/cycle) To South: 6 (48 B/cycle) From North: 4 (32 B/cycle) To North: 6 (48 B/cycle) East to West: 4 (32 B/cycle) West to East: 4 (32 B/cycle)
PL/Array Interface	From PL: 8 (64B/cycle @ PL clock) To PL: 6 (48 B/cycle @ PL clock)	From PL: 8 (64B/cycle @ PL clock) To PL: 6 (48 B/cycle @ PL clock)	From PL: 8 (64B/cycle @ PL clock) To PL: 6 (48 B/cycle @ PL clock)
Includes Control Module?
	No	No	Yes

Comparison of AIE Generations - Comparison of AIE Generations - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)