Accumulator Registers - Accumulator Registers - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

Accumulator registers are used to store the results of the vector data path and are 512-bit wide, they can be viewed as sixteen lanes of 32-bit data or eight lanes of 64-bit data. The main reason to have wider accumulator registers is to have high precision multiplication and accumulate over those results without bit overflows. The accumulator registers are prefixed with bm. Two of them are aliased to form a 1024-bit register prefixed with cm, and two cm can be aliased to form a 2048-bit register prefixed with dm.

Table 1. AIE-ML v2 Accumulator Registers
512-bit 1024-bit 2048-bit
bmll0 cml0 dm0
bmlh0
bmhl0 cmh0
bmhh0
... ... ...
...
... ...
...
bmll7 cml7 dm7
bmlh7
bmhl7 cmh7
bmhh7