AXI4-Stream Interconnect - AXI4-Stream Interconnect - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)
Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

Each AIE-ML v2 tile has an AXI4-Stream interconnect (alternatively called a stream switch) that is a fully programmable, a 64-bit AXI4-Stream crossbar, and is statically configured through the memory-mapped AXI4 interconnect. It handles backpressure and is capable of the full bandwidth on the AXI4-Stream. The AXI4-Stream interconnect has the following properties:

  • All elements of the switch data-path are 64-bit, which supports the transport of two 32-bit-words in parallel per cycle.
  • A TKEEP signal is added to support transfer of an odd number of 32-bit-words.
  • Stream parity is calculated on the 32-bit word and two parity bits transported with the data.
  • All external south, west, north, east, and stream-FIFO ports are capable of full throughput of 64-bit per cycle.
  • Sources and destinations of DMA which can run at full throughput of 64-bit per cycle.
  • Core, trace, and control-packet blocks have a 32-bit stream interface, so an adapter is placed for 32 <-> 64-bit conversion.
Figure 1. AXI4-Stream Switch High-Level Block Diagram

The tile ports are split into external ports and local ports. The external ports are south, west, north, and east. The local ports are core, DMA, FIFO, and trace. In the following description, a double-word refers to two adjacent 32-bit words on the stream, and in the case of TLAST=1 and TKEEP=0, a double-word refers to 32-bit word and the adjacent null-word.

  • External and local slave ports have two cycles of latency and four double-words of buffering.
  • Local master ports have one cycle of latency and two double-words of buffering.

Therefore, excluding packet switch arbitration overhead, the latency and buffering crossing the switch is external to external.

  • Local slave to local master: three cycles of latency, six double-words of buffering
  • Local slave to external master: four cycles of latency, eight double-words of buffering
  • External slave to local master: three cycles of latency, six double-words of buffering
  • External to external: four cycles of latency, eight double-words of buffering

The stream switch contains one 16-deep, 68-bit (64-bit data + 2-bit parity + 1-bit TLAST + 1-bit TKEEP) wide FIFO. Each stream port operates in either circuit-switched or packet-switched mode, selected by a packet-switching bit in the port’s configuration register. A port cannot use both modes at the same time. In packet-switched mode, multiple logical streams can share the same physical port and wires.

Table 1. AIE-ML v2 AXI4-Stream Tile Interconnect Bandwidth
Connection Type Number of Connections Data Width (Bits) Clock Domain (1 GHz) Bandwidth per Connection (GB/s) Aggregate Bandwidth (GB/s)
To North/From South 6 64 AIE-ML v2 array clock 8 48
To South/From North 4 64 AIE-ML v2 array clock 8 32
To West/From East 4 64 AIE-ML v2 array clock 8 32
To East/From West 4 64 AIE-ML v2 array clock 8 32
Note: The previous table assumes the slowest speed grade. Higher bandwidth can be achieve with a higher speed grade.

A circuit-switched stream has a one-to-one or one-to-many topology: a single source port feeds one or more destination ports, and all data entering the source is broadcast to all configured destinations. Latency is deterministic. When bandwidth is constrained, built-in backpressure throttles the source, which reduces overall performance.

Packet-switched streams can share ports with other packet-switched streams, which introduces potential resource contention and therefore non-deterministic latency. Each packet-switched stream uses a 5-bit stream ID that must be unique among streams sharing the same ports; this ID determines the packet’s destination(s). Packet switching supports flexible topologies, enabling any combination of single or multiple manager and subordinate ports within a stream.

A packet-switched packet has:

Packet header
Routing and control information for the packet
Data
Actual data in the packet
TLAST
Last word in the packet must have TLAST asserted to mark the end of packet
Table 2. Packet Header
Odd Parity 3'b000 Source Column Source Row 1'b0 Packet Type 7'b0000000 Stream ID
[31] [30:28] [27:21] [20:16] [15] [14:12] [11:5] [4:0]