The AIE-ML v2 tile has a local 16 KB of program memory with a data-width of 128-bit that can be used to store VLIW instructions. There are two interfaces to the program memory:
- Memory-mapped AXI4 interface
- AIE-ML v2 interface
An external manager can read or write to the program memory using the
memory-mapped AXI4 interface. The AIE-ML v2 tile has 128-bit wide interfaces to the
program memory to fetch instructions. The AIE-ML v2 tile can read from, but not write to, the program
memory. To access the program memory simultaneously from the memory-mapped AXI4 and AIE-ML v2 tile, divide the memory into multiple banks and access mutually exclusive parts of
the program memory. Arbitration logic is needed to avoid conflicts between accesses and
to assign priority when accesses are to the same bank. The core program memory load gets
priority and the other requests get a SLVERR if a
concurrent access is made to the program memory.