AIE-ML v2 Memory Tile Overview and Features - AIE-ML v2 Memory Tile Overview and Features - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)
Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

The AIE-ML v2 architecture incorporates memory tiles that provide substantial on-chip storage within the array, improving data locality and bandwidth while reducing the utilization of memory resources in the PL. The AIE-ML v2 memory tile is similar to the AIE-ML v2 tile but without the core and program memory. Instead, it features a larger (512 KB) high-density and high-bandwidth data memory, together with an integrated DMA. All DMA channels can access the local memory and a subset of them can directly access the memory in the nearest neighboring memory tiles to the east and west. A subset of DMA channels can directly access the memory in the nearest neighboring memory tiles to the east and west.

Figure 1. AIE-ML v2 Memory Tile Architecture

The AIE-ML v2 memory tile has the following functional blocks. They are either the same, or very similar to the equivalent blocks in AIE-ML v2 tile:

  • Memory
  • DMA
  • Locks
  • Stream switch
  • AXI4 switch
  • Control, debug, and trace
  • Events and event broadcast

The following are the features of the AIE-ML v2 memory tile:

  • Memory
    • 512 KB of memory arranged in eight physical banks. Each bank is 256-bit wide and 2K words deep.
    • ECC protected
  • AIE-ML v2 memory tile DMA
  • Six memory to stream (MM2S) DMA channels, each with:
    • 64-bit stream interface
    • 256-bit memory interface
    • Support for 4D tensor address generation
    • Support for inserting constant value into the stream data called constant padding.
    • Access memory and locks in the neighboring tiles (Channels 0 – 3)
    • Support task queue and task-complete-tokens with task repeat-count
    • Compression of zeros in data before sending on stream
    • Store incremental address offset between BD calls
    • TLAST suppress feature.
  • Six memory to stream (MM2S) DMA channels, each with:
    • 64-bit stream interface
    • 256-bit memory interface
    • Support for 4D tensor address generation
    • Access memory and locks in the neighboring tiles (Channels 0 – 3)
    • Support task queue and task-complete-tokens with task repeat-count
    • Decompression of stream data to re-insert compressed zeroes before storing to memory.
    • Store incremental address offset between BD calls
    • Support for out of order packet transfer
    • Support for Finish on TLAST
  • Buffer descriptors (BD): 48 shared buffer descriptors across all 12 DMA channels
  • Stream switch:
    • Shares the same design as AIE-ML v2 tile with 17 manager and 18 subordinate ports.
    • The data path has 64-bit throughput which supports two 32-bit words in parallel per cycle.
    • TKEEP signal added to support transfer of an odd number of 32-bit-words.
    • North and south ports and DMA can run at full throughput of 64-bit per cycle.
    • Trace and control ports have 32-bit interface and adapters are placed to convert them to 64-bit.
  • Lock module:
    • Accessible from local and neighboring AIE-ML v2 memory tile DMA channels
    • There are 64 semaphore locks and each lock state is 6-bit unsigned.
  • Additional control and status registers:
    • Events, event actions, event broadcast, and combo events
    • Task-complete-tokens logic
  • Configuration/debug interconnect (AXI4)
    • 1 MB address space per tile
    • Stream control-packet support
  • Debug and trace
    • Event trace streams
    • Six performance counters and a 64-bit tile timer