Each memory tile has 512 KB of memory formed from eight banks of 64 KB. Each bank is 256-bit wide and 2K words deep. Each bank can be accessed by ten read and ten write interfaces.
The memory tile read interfaces are:
- AXI4 read (including control packets)
- One MM2S interface from the MM2S channels in the neighboring memory tile to the left
- 6x local MM2S channels [0 – 5]
- One MM2S interface from the MM2S channels in the neighboring memory tile to the right
- ECC scrubber
Figure 1. Memory Tile Memory Read Interfaces
The memory tile write interfaces are:
- AXI4 write (including control packets)
- One MM2S interface from the MM2S channels in the neighboring memory tile to the left
- 6x local S2MM channels [0 – 5]
- One MM2S interface from the MM2S channels in the neighboring memory tile to the right
- ECC scrubber/zeroization
Figure 2. Memory Tile Memory Write Interfaces
DMA S2MM channels (0 – 3) and MM2S channels (0 – 3) can access the local memory banks and the memory banks of the Memory-tile to the east and the west. The memory in memory tile supports bank interleaving. Interleaving is done at 256-bit granularity, such that sequential 256-bit accesses map to different banks and wrap around after the eight banks (every 256B). The memory tile banks have ECC protection and ECC scrubbing.