AIE-ML v2 Memory Tile Locks Module and Stream Switch - AIE-ML v2 Memory Tile Locks Module and Stream Switch - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

The memory tile semaphore locks are identical to those in the AIE-ML v2 tile. The memory tile supports up to 64 semaphore locks each carrying a 6-bit unsigned lock state. All the locks are accessible from local DMA channels and from S2MM and MM2S channels 0 – 3 from both east and west neighboring memory tiles. Locks are also accessible through memory mapped AXI4.

The memory tile stream switch is similar to the tile stream switch with 17 manager ports and 18 subordinate ports. Unlike the tile stream switch, this design has no east or west stream ports.