The AIE-ML v2 memory module (shown in the following figure) contains eight memory banks, two input streams to memory map (S2MM) DMA, two memory-map to output DMA streams (MM2S), and a hardware synchronization module (locks).
Figure 1.
AIE-ML v2 Memory
Module
- Memory Banks
- The AIE-ML v2 data memory is 64 KB, organized as eight memory banks, where each memory bank is a 256 word x 256-bit single-port memory. From a programmer's perspective, a pair of hardware banks are interleaved at 256-bit granularity to present four programmer banks each being 512-bit wide. Banks 0 and 1 have ECC error correction. Banks 2–7 have parity protection.
- Memory Arbitration
- Arbitration is performed independently for each bank with parallel accesses to different banks supported. Therefore, there are eight independent arbiters per tile DM. Arbitration is between all accessors with active requests. The arbitration is hierarchical, with accessors arranged into fixed groups.
- Tile DMA Controller
- The tile DMA connects to the AIE-ML v2 stream switches with
two incoming and two outgoing streams. It consists of two modules: S2MM, which
writes 64-bit stream data to memory, and MM2S, which reads 64-bit data from
memory to a stream. DMA transfers are defined by buffer descriptors; the
controller supports 16 descriptors, accessible and configurable from any
memory-mapped AXI4 manager. Each descriptor contains all parameters for a
transfer and can optionally chain to the next descriptor for continuous
operation. The controller also manages 16 locks used for synchronization between
the AIE-ML v2 array, the DMA, and any external memory-mapped AXI4 managers. Descriptors can be configured to use these locks
through the same AXI4 interface. The DMA datapath sustains a
throughput of two 32-bit words per cycle.
The DMA controller supports:
- 4D tensor address generation (including iteration-offset)
- Task queues and task complete tokens
- S2MM finish on
TLASTand handling of out-of-order packets - Decompression on the two S2MM channels
- Compression to the two MM2S channels
- Lock Module
- The AIE-ML v2 memory module contains a lock module to achieve synchronization amongst the AIE-ML v2s, tile DMA, and an external memory-mapped AXI4 interface manager (for example, the processor system (PS)). The AIE-ML v2 features 16 semaphore locks, each carrying a 6-bit unsigned as state. The lock module handles lock requests from the AIE-ML v2s in all four directions, the local DMA controller, and memory-mapped AXI4.