AIE-ML v2 Interfaces - AIE-ML v2 Interfaces - AM027

The AIE-ML v2 has multiple interfaces. The following block diagram shows the interfaces.

Data Memory Interface

The AIE-ML v2 core can access data memory modules on all four directions. They are accessed as one contiguous memory. The AIE-ML v2 core has two 512-bit wide load units and one 512-bit wide store unit. From the AIE-ML v2 perspective, the throughput of each of the loads (two) and store (one) is 512 bits per clock cycle.

Program Memory Interface

This 128-bit wide interface is used by the AIE-ML v2 core to access the program memory. A new instruction can be fetched every clock cycle.

Direct AXI4-Stream Interface

The AIE-ML v2 core has one 32-bit input AXI4-Stream interface and one 32-bit output AXI4-Stream interface. Each stream allows the AIE-ML v2 core to have a four-word (128-bit) access every four cycles, or a one-word (32-bit) access every cycle.

Cascade Stream Interface

The 512-bit accumulator data from one AI Engine can be forwarded to another by using these cascade streams to form a chain. Using this stream, the core can transfer accumulator data to the next core. There is a small FIFO which accumulates up to two 512-bit wide words on both input and output streams. This allows the storing of four accumulator words in FIFO between each AIE-ML v2 core.

Debug Interface

This interface is able to read or write all AIE-ML v2 core registers over the memory-mapped AXI4 interface.

Hardware Synchronization (Locks) Interface

This interface allows synchronization between two AIE-ML v2s or between an AIE-ML v2 and DMA. The AIE-ML v2 can access the lock modules in all four directions. There is also added support for semaphore locks.

Stall Handling

An AIE-ML v2 can be stalled due to multiple reasons and from different sources. Examples include external memory-mapped AXI4 manager (for example, PS), lock modules, empty or full AXI4-Stream interfaces, data memory collisions, and event actions from the event unit.

AIE-ML Event Interface

This 16-bit wide EVENT interface can be used to set different events. The tile provides 128 internal core module and 128 memory module events. Each event has a unique number.

Tile Timer

The input interface to read the 64-bit timer value inside the tile.

Execution Trace Interface

A 32-bit wide interface where the AIE-ML v2 generated packet-based execution trace can be sent over the AXI4-Stream.