The AIE-ML v2 configuration process writes a programmable device image (PDI) produced by the bootgen tool into AIE-ML v2 configuration registers. The AIE-ML v2 configuration is done over memory-mapped AXI4 via the NoC. For more information on generating a PDI with the bootgen tool, refer to Bootgen User Guide (UG1283).
The following table summarizes the reset controls available for the global AIE-ML v2 array.
| Type | Trigger | Scope |
|---|---|---|
| Internal power-on-reset | Part of boot sequence | AIE-ML v2 array |
| System reset | NPI input | AIE-ML v2 array |
| INITSTATE reset | PCSR bit | AIE-ML v2 array |
| Array soft reset | Software register write over NPI | AIE-ML v2 array |
| AIE-ML v2 tile column reset | Memory-mapped AIE-ML register bit in the array interface tile | AIE-ML v2 tile column |
| AIE-ML v2 core reset | Memory-mapped AIE-ML v2 register bit in the core tile | |
| AIE-ML v2 array interface reset | From NPI register | AIE-ML v2 array interface tile |
The combination of column reset and array interface tile reset (refer to AIE-ML v2 Array Hierarchy) enables a partial reconfiguration use case where a sub-array that comprises AIE-ML v2 tiles and array interface tiles can be reset and reprogrammed without disturbing adjacent sub-arrays. The specifics of handling the array splitting and adding isolation depend on the type of use case (multi-user/tenancy or single-user/tenancy multiple-tasks).