AIE-ML v2 Array Interface to NoC and PL Resources - AIE-ML v2 Array Interface to NoC and PL Resources - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English
  • A control module used for setting up the application, orchestrate execution and data movement during runtime for each column. This is also used to allow synchronization with external host.
  • Configuration through the memory-mapped AXI4 interface of local registers and control module.
  • Streaming interconnect provides routing between PL resources and array tiles.
  • AIE-ML v2 to programmable logic (PL) interface that provides asynchronous clock-domain crossing between the AIE-ML v2 clock and the PL clock.
  • AIE-ML v2 to NoC interface logic to the NoC manager unit (NMU) and NoC subordinate unit (NSU) components.
  • Hardware synchronization primitives leverage features from the AIE-ML v2 tile locks module.
  • Debug, trace, and profile functionality that leverage all the features from the AIE-ML v2 tile.