AIE-ML v2 Array Hierarchy - AIE-ML v2 Array Hierarchy - AM027

Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)

Document ID
AM027
Release Date
2025-10-23
Revision
1.1 English

The AIE-ML v2 array is made up of AIE-ML v2 tiles, one or two rows of AIE-ML v2 memory tiles, and AIE-ML v2 array interface-tiles (the last row of the array). The following figure shows a conceptual view of the complete tile hierarchy associated with the AIE-ML v2 array. See AIE-ML v2 Tile Architecture, AIE-ML v2 Array Interface Architecture, and AIE-ML v2 Architecture for detailed descriptions of the various tiles.

Figure 1. Hierarchy of Tiles in an AIE-ML v2 Array