eMMC Interface Signals - eMMC Interface Signals

eMMC Interface Signals - eMMC Interface Signals - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The following table lists the eMMC I/O interface signals. For boot pin planning, see MIO Boot Interfaces. The eMMC MIO signals are also listed in the first PMC MIO signal table in the MIO Boot Interfaces. The eMMC I/O interface is available on the PMC MIO pins and on the PL EMIO port signals. All modes might not be supported for the PL EMIO interface.

The following table lists the eMMC interface signals. The MIO pin number assignments are shown in the MIO-at-a-Glance Tables.

Table 1. eMMC Interface Signals
Signal Name	Description	MIO
Signal Name	Description	MIO-at-a-Glance Table	I/O
EMMC_CLK	Clock output	CLK	O
EMMC_CMD	Command	CMD	O
EMMC_DATA[0]	Data I/O pin for 1-bit, 4-bit, and 8-bit data interfaces	D [0]	I/O
EMMC_DATA[3:1]	Data I/O pins for 4-bit, 8-bit data interfaces	D [3:1]	I/O
EMMC_DATA[7:4]	Data I/O pins for 8-bit data interface	D [7:4]	I/O
Independently Route-able Signal¹
EMMC_RST	Reset output that resets the flash device	RST	O
The independently route-able signal is essentially DC and does not necessarily need to be in the same pinout group as the I/O, clock, and command signals.